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Altera_Forum
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15 years ago

Divider maximal frequency

Hello everyone, I am currently working on Altera's DE2 board with QuartusII 9.0 sp2 Web Edition software. I'm implementing various architectures of dividers on DE2 board FPGA device (EP2C3...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Oh thank you very much men !

Your reply just gave me the idea to use registers on divider inputs and outputs. The problem is solved. I get 28.85 MHz for maximal operational frequency.

Thank you very much guys, you are unbelieveable ! ;)

See you...