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Altera_Forum
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13 years agoi have one phase encoder ...
i wrote this program but got an errore about the multiplication, how can i alternate that by synthessisable way ?? library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity encoder is port( CLK : in std_logic; sig : in std_logic ; reset : in std_logic; req_dist: buffer std_logic_vector(8 downto 0) -- till 5 meter. ); end entity encoder; architecture arc_encoder of encoder is signal tmp_sig : std_logic; signal counter : std_logic_vector(8 downto 0); signal distance : std_logic_vector(8 downto 0); begin process(CLK) begin if (reset='1') then counter <= (others => '0'); else distance <= req_dist*24 and "111000000"; ------------------------------------------------------ HERE IS THE ERRORE end if; if rising_edge(sig) then if (counter < distance) then counter <= counter+1; else counter <= counter; end if; end if; end process; end architecture arc_encoder;