Discussion points....

Hi all,

So I've finalised my code for a uni project I'm studying. I'm currently writing up my report on how I developed my code and thought it would be good to end it with some discussion points/ideas for improvements. However because I'm new to VHDL I don't really know what possible points I could raise (I'm at the limit of my understanding!), and as I'm distance learning I don't really have anyone to bounce ideas off. I don't think I need to change my code as such, just discuss other options and say why they would have been better or worse. Does anyone have any suggestions?

The code just sets a simple repeating pattern of outputs based around an up-counter, I've pasted it below:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.std_logic_unsigned.all;

entity seq is

port (clk : in std_logic;

enable : in std_logic;

reset : in std_logic;

a,b,c,d,e,f : out std_logic);

end;

architecture behaviour of seq is

signal count : integer range 0 to 5;

signal vector : std_logic_vector (5 downto 0);

begin

process(clk, enable, reset)

begin

if reset = '1' then

count <= 0;

elsif falling_edge (clk) then

if enable = '1' then

if count < 5 then

count <= count + 1;

case count is

when 0 => vector <= "001100";

when 1 | 5 => vector <= "011110";

when 2 | 4 => vector <= "110011";

when 3 => vector <= "100001";

end case;

else count <= 0;

end if;

end if;

end if;

end process;

a <= vector(5);

b <= vector(4);

c <= vector(3);

d <= vector(2);

e <= vector(1);

f <= vector(0);

end behaviour;