Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Disabling STDOUT in timequest

Hey Altera people, Im writing some tcl scripts to get some low level delay information from quartus. Every time I do a report_path command I get a bunch of output printed on the timequest conso...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Yes constraining the FPGA design using these methods is a good option however I have to account for the possibility that we will have an existing FPGA bitstream applied to modified hardware.

In this case we do not want to constrain the FPGA design any more, but would like to know if it conforms to the new hardware. In effect it would close the loop. Maybe.