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AEsqu's avatar
AEsqu
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5 years ago

Disable Quartus timing analyzer inverted clock

Hello, Is there a way to disable the inverted clock latch analysis in quartus 20.1 for arria 10? I had no such inverted clock analysis with the same design using Quartus 13.1 on stratix 3 , wit...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

Can you post your SDC? This is pretty strange. It also looks like all the failures are on paths that are fanning in to a single clock enable input which seems odd. Can you post any of the HDL for this part of the design?

#iwork4intel

AEsqu's avatar
AEsqu
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5 years ago

I cannot share RTL code.

I use this kind of constraints for now to remove those timing checks:

set_false_path -fall_to [get_clocks {mcu_clk}] -from [get_registers {*|u_rfd_clockshop|i_apb_if|s_sw_all_periph_reset_en}]


set_false_path -rise_from [get_clocks {mcu_clk}] -to [get_registers {*|u_flash_subsys|A_ip_pflash640k_atfc|u_controller|u_fmc_if|start_gate|u_cgate|ClkEnable*}]

  • AEsqu's avatar
    AEsqu
    Icon for Contributor rankContributor
    5 years ago

    Here is the SDC.

    For this run, variables are set to:

    $is_a_quartus_only_project == "0"

    $current_project == "Achilles_arria_X"

    $is_a_quartus_project == "1"