Disable DSB block input and output register moving

--- Quote Start ---

Hi,

I have an issue with DSP blocks that they are inferred by the synthesiser but the input and output registers are placed into logic. After that during Place & Route it's decided by the tool where to locate them, either inside the DSP block or outside (which is the case usually).

I have to reach the lowest logic register usage so I must keep them inside the DSP block but haven't found any parameter to set for this.

My ideas were to disable it in the settings but haven't found an option. Also thoght to add some constraint to the VHDL file that limit the allowed logic register cound on module level, but also don't know about it.

Is there anybody who has experience with it, or has any idea to try?

Thanks,

Gyula

--- Quote End ---

assignments => auto packed registers => choose an option (depend on device).

If you have not applied timing constraints to the design, then Quartus will place registers where ever it likes.

If you want to confirm that your logic will fit inside a DSP block, then you can use a LogicLock region and place the logic into that region. For example, I recently wanted to confirm that a DSP Block could be used to implement three multipliers, however, Quartus would use 3 DSP blocks, since it had available resources. Using a LogicLogic region to restrict Quartus's options was the solution.

The easiest way to create a region is;

1. Synthesize your design.

2. In the Hierarchy tab, select your component, right-click and select LogicLock Region -> Create New LogicLock Region

3. Then use Tools->Chip Planner to change the properties of that region, eg., fix it to a location that only includes a DSP block

4. Resynthesize the design.

5. Iterate.

Play with the GUI and read the Quartus LogicLock documentation and you'll get the hang of it.

Cheers,

Dave

Hi,

Thank you for the tips. I couldn't try the logic lock to dsp block because there are many blocks occupied by the dedicated functionality it's over hundreds of the same thing into separate dsp blocks. The attribute may did something but there are still registers moving outside in various numbers, depending on the code. Eventually my last source generates less than it was. So its' still a living inssue. I also tried to place the attribute into the wrapper entity but the result is the same.

Thanks,

Gyula

--- Quote Start ---

I couldn't try the logic lock to dsp block because there are many blocks occupied by the dedicated functionality it's over hundreds of the same thing into separate dsp blocks.

--- Quote End ---

For the purpose of testing, just create one instance and assign it to a logic lock region. If that fixes your problem, then at least you know a solution.

Rysc has a tutorial on the wiki that uses multiple logic lock regions for DSP blocks containing duplicated logic.

http://www.alterawiki.com/wiki/tips_for_incremental_compilation_and_logiclock

Cheers,

Dave