Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

direct DDR communication via VHDL/Verilog

Hello all, I would like to setup a kernel with an RTL library that directly access the DDR. This kind of work is illustrated here, in example 2: https://www.altera.com/support/support-resources...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Actually I have the same problem. So far, I can find all necessary modules, for example lsu_top in $QUARTUS_ROOT/hld/ip, and run module level simulation. But I don't understand how can the module communicate with BSP env, like how does the BSP knows when the function is stopped.