differential pin spacing requirements

For inquiring minds, here is Altera's response. It is a valid approach as long as it's a low speed interface. You can either use the 3R network, or choose regular LVDS standard and verify the violating pins are low toggle rate, then apply appropriate max toggle constraints.

The LVDS_E_3R is an emulated LVDS output type and not a true differential output, so it’s one way of side-stepping the problem. It utilizes single-ended output buffers with an external termination network to emulate a differential output. It’s valid in bank 2, since it’s able to implement either I/O type in that bank. Although either one would work, the true LVDS output will provide better signal integrity and a faster output data rate. Do you still have the flexibility of moving around pins in your design? If so, you might wish to either move the non-differential signals further away from the differential signals, or place signals that are reasonably static (such as reset signals, reasonably static status signals, etc.) nearby. You can then apply an “I/O Maximum Toggle Rate” setting to allow single-ended signals to be placed closer to differential ones.