Occasional Contributor
Occasional ContributorI've attempted the 'dummy' software cross feeding a 1 and 0 to the data in H & L of the altddio_bidir to generate 2 outputs, a p&n IO pad. I now get this new error instead:
Error (169008): Can't turn on open-drain option for differential I/O pin DDR3_DQS_n[0]
I am not sure if this is any closer, but at least the DDR3_DQS_p[0] pins are still labeled as differential and they made it through.
Oops, the IO wasn't assigned. I still get the same tri-state error.
Occasional ContributorOk, I tried using 'altiobuf_bidir' which has both differential and bidirectional capability, yet Quartus says:
Error (176202): The differential I/O standard Differential 1.5-V SSTL cannot be used on the pin DDR3_DQS_p[0], because the specified pin uses a tri-stated output buffer.
Even worse, I cannot simulate in ModelSim when using the 'altiobuf_bidir'. It is not a recognized function.
It would seem Altera's Mem-phy seems to access the DQS pins as bidirectional differential I/O standard Differential 1.5-V SSTL fine, but I am at a loss as how to do so directly.
Now I know I can use something like altdq_dqs2, however, it is not compatible with Cyclone IV/III, or others. Their older altdqs doesn't support differential and wont work on newer cyclones and max 10 fpgas.
ContributorHi
Which version of Quartus software are you using to implement altddio_bidir with MAX10 device ?
As far as I see I do not find the altddio_bidir in IP Catalog when I set the device as MAX10.
Occasional ContributorQuartus 15 and 20.1.
You are correct that it does not show up in the IP catalog if you look.
But if you have it in your existing code, how are you supposed to know?
It gets worse as it does function completely in simulation, both RTL and Gate level.
It also funchtions in hardware when in input mode. It's when your coded switches it to output that the IO is output, but dead. But the simulation says it's working and Quartus does not complain at all.
All these little Quartus bugs waste weeks of debugging time.
I have switched it to 'altera_gpio_lite' which has fixed the output and differential DQS functionality. Now I have a new problem. Using 'altera_gpio_lite', ModelSim gives me an entire stream (like 20x) of:
** Warning: (vsim-3722) altera_gpio_lite.sv(908): [TFMPC] - Missing connection for port 'nsleep'.
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'ibuf'. Expected 4, found 3.
And Quartus Prime 20.1 give these warnings:
Warning (10036): Verilog HDL or VHDL warning at altera_gpio_lite.sv(82): object "nsleep_in" assigned a value but never read
How do I fix this? I'm not even calling 'ibuf', it's what was generated by your IP Megafunction library.
When I call the 'altera_gpio_lite', I do have:
.nsleep ({16{1'b0}});.....
My code should be clean, free of these warnings.
ContributorHi
When I see the GPIO Lite IP opening with MAX10 device the GUI shows the nsleep is not available in selected device. I assume if you leave the port open the Quartus will not generate any warnings or you can safely ignore the warning messages.
