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Altera_Forum's avatar
Altera_Forum
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17 years ago

different clock'event on the same file

Is it possible to write 2 processes, one activated by clock rise and the other by clock fall that could write the same register? I'm trying to construct a register file that may receive 2 sources of ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Don't think of VHDL, but the underlying hardware. There are no registers that are triggered of both edges(in any FPGAs), so whether VHDL could do it or not is irrelevant. You need two separate registers to clock the data, one rising and one falling, and then your own arbitration mux to determine which one is valid.