Forum Discussion
Altera_Forum
Honored Contributor
8 years agoAn Altera/Intel FPGA has multiple Block RAMs, each with a size of 20Kbits, and 2 ports. "RAM blocks" shows the number of M20K blocks with at least one occupied port. "Memory bits" shows the total number of bits among all the M20K blocks that is occupied by valid data.
512 floats is 16Kbits which is far too big to be implemented using registers, and would require one M20K per access. External memory accesses are always coupled with a private on-chip cache which could potentially prevent redundant accesses from going to external memory, and improve performance. Mixing "volatile" and "constant" does not make sense; something that is constant cannot be volatile. Caches for non-constant buffers can be disabled by using volatile. For constant buffers, a different cache is used. Check "Intel FPGA SDK for OpenCL Best Practices Guide, Section 7.3.1" for more info about how you can control the size of the constant cache. If you are manually loading data to local memory, you do not need the cache anymore, and you can disable it.