DFF Toggle Flop / PLL clock division impact on timing

Quartus II won't ever use something as a clock. It's going to be something in your code. You can trace it forward in the RTL viewer, or another trick is to run the following in TimeQuest:

derive_clocks -period 10.0

This will constrain these clocks as 10ns clocks and they'll be related to everything. Basically at this point the timing analysis is useless, but you can do a report_timing to these two new clock domains and you'll see which registers are using these state-bits as clocks. You can then look through the code and figure it out from there.