DFF Toggle Flop / PLL clock division impact on timing

When sending data between asynch clock domains, two things can happen:

1) The data can be changing just as the receiving register clocks it, causing the register to go metastable. Doesn't happen too often, but the metastable output can trickly down and cause failures elsewhere.

2) When sending more than one bit that are analyzed together, they will all arrive at slightly different times. So if the receiving registers are at "0000" and you send "1111", that transition may occur around a clock edge, so some registers clock in the 1s and the others don't. Your data is no longer valid. Understnading clock domains and handling them is one of the major things FPGA/ASIC designers need to understand, and it takes a while.