DFF Toggle Flop / PLL clock division impact on timing

yeah...Thanks Rysc...

I was thinking the 2.66667 MHz (T=375ns) is alot slower than the 40MHz one...so maybe I can cut some corner by passing the signal directly...

and yeah..I should set the clock group asynchronously...TimeQuest probably looking at the 40Mhz and the 2.66667Mhz and figured they are related (x15)...so no timing issues were reported at first..now..the PLL introduce phase difference and timing issues show up....

...more debugging...more correcting....seems endless process :)

I'll try that and if further question, I'll post it here..

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You seem to be sending logic between clock domains without synchronizing them, going through a FIFO, etc. Are they really related? Even though the CC?CLK clocks are slow, you generally can't just send data to them asynchronously.

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