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Altera_Forum
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17 years ago

DFF Toggle Flop / PLL clock division impact on timing

Hello all again... :) Alright..So finally, I managed to make my project compiled and synthesized at 40MHz without any setup/hold timing issues....My last problem comes as my clock input would b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

You seem to be sending logic between clock domains without synchronizing them, going through a FIFO, etc. Are they really related? Even though the CC?CLK clocks are slow, you generally can't just send data to them asynchronously.