Determining path for cell in netlist

TimeQuest shouldn't do this, by the way of the way create_generated_clocks works. Note that the -source is a node and not a clock. Basically this takes the "ideal" clock that exists on that node in the design. As a good example, when you run derive_pll_clocks, look at the Info messages to see what the -source is for the PLL output clocks. It is not the incoming clock port, but the actual inclock pin of the PLL. Now, you could modify this to be the top-level clock port and you would get identical results. This is because you only take the waveform along that clock, and TimeQuest then calculates the delay to that point(in the documentation they refer to it as latency). This is always confusing, but it is a much more powerful way to do it, more flexible, and gives the correct results.

But in your case, you chose a node before the PLL. So for example, let's say osc_CLK0 was a 10ns clock, and the PLL divided it down to a 20ns clock, and then your ripple clock divided it again to a 40ns clock. If your generated_clock was -divide_by 2, but you had the -source by osc_CLK0, we would be taking the 10ns clock and dividing it by 2, when you really want to take the 20ns clock and dividing it by 2.

(I'm probably making this more confusing, but it's more information as to how this works, which may prove useful).