Determining path for cell in netlist

Brad,

Yes, I am used to doing this in an ASIC. With an ASIC, you can create as many generated clocks as you'd like, and then assign the output to a clock buffer, which then gets converted to a clock tree by the layout engineer. The clock tree is balanced across the chip for minimal clock skew. Typically, all clocks are created in a central clock and reset block, something that I highly recommend.

The design I am working with was inherrited, so I have no control over the logic. The generated clocks are driving local area logic, and are not used as a global clock. All global clocks in the design are driven from the PLLs in the Nios II processor. Its true there will be some clock skew, but from what I've seen so far, this does not appear to be a problem. However, to do sure, I need to create the generated clocks correctly, inside TimeQuest, hence the start of this thread.

As for using the Netlist Viewer inside TimeQuest, I don't remember if I used the compatibility mode checkbox as you recommended.....I will check on this again tomorrow morning. For what I am trying to accomplish, I should be able to create a generated clock on the output pin of the device that is driving the clock, which I would typically use the get_pins command. For now, I will use get_keepers, unless you can give me a good argument against it.