Hello, I am trying to get a Time to digital converter to work in my FPGA (like many before but no one actually posted the solution). I know that the base for everything is the LAB, containing 16 LE, which each has 2 LUT and a DFF and some other control logic. My gate level simulation is working but i am confused with the use of the CARRY_SUM primitive. If i understand correctly you have to place this primitive between the registers you want to connect through the internal (fast) carry path. e.g. Logic_1(out)-> CARRY_SUM => Logic_2(in) and in synthesis it is supposed to use the carry line. However it doesn't. It uses an input of the LUT which simulates with a delay between 300-800ps. Carry is supposed to be well below 100ps. The Cookbook uses "stratixii_lcell_comb" but i couldn't find any clear documentation nor if it also works in Cyclone. And i am using VHDL and cookbook examples are all verilog. :( Can anyone provide an example of successful usage of the CARRY_SUM primitive?

--- Quote Start --- no one actually posted the solution --- Quote End --- I noticed that too. Did you try to contact the contributors? I didn't yet use the carry_sum primitive, in so far I can't help you with it. I guess, the trick is (same thing with xx_lcell_comb primitives), that cin and cout can't be wired to regular logic, only connected to each other. To start a carry chain, you need a logic cell, possibly a dummy logic cell. --- Quote Start --- The Cookbook uses "stratixii_lcell_comb" but i couldn't find any clear documentation nor if it also works in Cyclone. --- Quote End --- You'll have noticed that the wysiwyg libraries contain also cyclonexx_lcell_comb primitives. The lut_mask coding is unfortunately undocumented, as for stratix. You can e.g. review valid lut_mask codes in the quartus floor planner. I append an priority bit encoder example using cycloneiii_lcell_comb, unsupported as is. The example is related to this previous thread http://www.alteraforum.com/forum/showthread.php?t=27881 Regards, Frank

Thanks, i think you pointed me to the right direction. I found a documentation which wasn't easy to google but describes how to set the LE in arithmetic mode and how to define the LUT tables (attached). I will try to keep the thread updated.

Thanks for the document. According to the advanced synthesis cookbook, similar information should be available for Stratix.

--- Quote Start --- Thanks, i think you pointed me to the right direction. I found a documentation which wasn't easy to google but describes how to set the LE in arithmetic mode and how to define the LUT tables (attached). I will try to keep the thread updated. --- Quote End --- It's very useful for TDC design. I'm also search these detail materials about LE, but i found nothing. BTW, i have finished TDC design with altera's devices as attahced files show. The cin to cout delay should be 51ps from TimeQuest report. And the actual time should be different because of the gaps inside LAB and between LABs. We can see that the delay cell's min delay time is below 20ps, however, the max is about 170ps.

Also, i found that we can't use carry and carry_sum directly in new version QII software. They will be optimized away when the project is compiled! It's very strange. I found some comments from altera's paper that we should can use them. But that paper is very old, maybe it is ok in old version QII. Even though, LCELL still can be used.

Designing with low level primitives | Altera Community

14 Replies

Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
google for "Cycloneii_le_wys.pdf" and on the first hit u can find those documents.
--- Quote End ---

Or download the QUIP Toolkit from Altera. Sometimes the obvious is hidden somehow, thanks for giving me a leg up.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
google for "Cycloneii_le_wys.pdf" and on the first hit u can find those documents. (somehow not allowed to post links here...)
That is where I found this files and they also have the stratix version.

BTW, considering some papers, it seems like they do not use the cin cout ports(through 1 LUT), but just the multiplexers. Compare the appended paper with the LCELL circuit.

However this was just a minor idea of mine and I had to move on to a different project. I will try to pick it up again once i have time.
--- Quote End ---

Hi SiA_Schumi:

Thanks for you information.

The doc you attached compare several tdc implementation method. One of them, J.Wu has designed 10ps TDC using CII. I also used his method to implement my tdc. I have posted the test results in my previous posts. His method just use carry-chain.

FvM said that he want implement a real delay-line. But i don't think that there is absoluted real delay-line ^0^. We can't avoid "jitter" inside delay-line, but we can improve.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
Or download the QUIP Toolkit from Altera. Sometimes the obvious is hidden somehow, thanks for giving me a leg up.
--- Quote End ---

Hi FvM:

Thanks, I have download QUIP Toolkit 9.0 from Altera.
Altera_Forum
Honored Contributor
10 years ago
--- Quote Start ---
I noticed that too. Did you try to contact the contributors?

I didn't yet use the carry_sum primitive, in so far I can't help you with it. I guess, the trick is (same thing with xx_lcell_comb primitives), that cin and cout can't be wired to regular logic, only connected to each other. To start a carry chain, you need a logic cell, possibly a dummy logic cell.

You'll have noticed that the wysiwyg libraries contain also cyclonexx_lcell_comb primitives. The lut_mask coding is unfortunately undocumented, as for stratix. You can e.g. review valid lut_mask codes in the quartus floor planner.

I append an priority bit encoder example using cycloneiii_lcell_comb, unsupported as is.

The example is related to this previous thread http://www.alteraforum.com/forum/showthread.php?t=27881

Regards,
Frank
--- Quote End ---

Hi Frank,

it is quite old post, I hope you will see my question... The problem is that if I adapt the design for Cycloneii then it is compiled only on RTL level however nothing at synthesis... I did try every think (I think), changing LUT mask, re-configuring the cells, nothing works... Any idea? It is strange to me from the moment Altera says that Cycloneiii cell is exactly the same as Cycloneii and wysiwyg parameters are the same...

Thanks,
Alexander

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Designing with low level primitives

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