Hello, I am trying to get a Time to digital converter to work in my FPGA (like many before but no one actually posted the solution). I know that the base for everything is the LAB, containing 16 LE, which each has 2 LUT and a DFF and some other control logic. My gate level simulation is working but i am confused with the use of the CARRY_SUM primitive. If i understand correctly you have to place this primitive between the registers you want to connect through the internal (fast) carry path. e.g. Logic_1(out)-> CARRY_SUM => Logic_2(in) and in synthesis it is supposed to use the carry line. However it doesn't. It uses an input of the LUT which simulates with a delay between 300-800ps. Carry is supposed to be well below 100ps. The Cookbook uses "stratixii_lcell_comb" but i couldn't find any clear documentation nor if it also works in Cyclone. And i am using VHDL and cookbook examples are all verilog. :( Can anyone provide an example of successful usage of the CARRY_SUM primitive?

--- Quote Start --- no one actually posted the solution --- Quote End --- I noticed that too. Did you try to contact the contributors? I didn't yet use the carry_sum primitive, in so far I can't help you with it. I guess, the trick is (same thing with xx_lcell_comb primitives), that cin and cout can't be wired to regular logic, only connected to each other. To start a carry chain, you need a logic cell, possibly a dummy logic cell. --- Quote Start --- The Cookbook uses "stratixii_lcell_comb" but i couldn't find any clear documentation nor if it also works in Cyclone. --- Quote End --- You'll have noticed that the wysiwyg libraries contain also cyclonexx_lcell_comb primitives. The lut_mask coding is unfortunately undocumented, as for stratix. You can e.g. review valid lut_mask codes in the quartus floor planner. I append an priority bit encoder example using cycloneiii_lcell_comb, unsupported as is. The example is related to this previous thread http://www.alteraforum.com/forum/showthread.php?t=27881 Regards, Frank

Thanks, i think you pointed me to the right direction. I found a documentation which wasn't easy to google but describes how to set the LE in arithmetic mode and how to define the LUT tables (attached). I will try to keep the thread updated.

Thanks for the document. According to the advanced synthesis cookbook, similar information should be available for Stratix.

--- Quote Start --- Thanks, i think you pointed me to the right direction. I found a documentation which wasn't easy to google but describes how to set the LE in arithmetic mode and how to define the LUT tables (attached). I will try to keep the thread updated. --- Quote End --- It's very useful for TDC design. I'm also search these detail materials about LE, but i found nothing. BTW, i have finished TDC design with altera's devices as attahced files show. The cin to cout delay should be 51ps from TimeQuest report. And the actual time should be different because of the gaps inside LAB and between LABs. We can see that the delay cell's min delay time is below 20ps, however, the max is about 170ps.

Also, i found that we can't use carry and carry_sum directly in new version QII software. They will be optimized away when the project is compiled! It's very strange. I found some comments from altera's paper that we should can use them. But that paper is very old, maybe it is ok in old version QII. Even though, LCELL still can be used.

Designing with low level primitives | Altera Community

14 Replies

Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
no one actually posted the solution
--- Quote End ---

I noticed that too. Did you try to contact the contributors?

I didn't yet use the carry_sum primitive, in so far I can't help you with it. I guess, the trick is (same thing with xx_lcell_comb primitives), that cin and cout can't be wired to regular logic, only connected to each other. To start a carry chain, you need a logic cell, possibly a dummy logic cell.

--- Quote Start ---
The Cookbook uses "stratixii_lcell_comb" but i couldn't find any clear documentation nor if it also works in Cyclone.
--- Quote End ---

You'll have noticed that the wysiwyg libraries contain also cyclonexx_lcell_comb primitives. The lut_mask coding is unfortunately undocumented, as for stratix. You can e.g. review valid lut_mask codes in the quartus floor planner.

I append an priority bit encoder example using cycloneiii_lcell_comb, unsupported as is.

The example is related to this previous thread http://www.alteraforum.com/forum/showthread.php?t=27881

Regards,
Frank
priority_bit.vhd1 KB
Altera_Forum
Honored Contributor
12 years ago
Thanks, i think you pointed me to the right direction. I found a documentation which wasn't easy to google but describes how to set the LE in arithmetic mode and how to define the LUT tables (attached). I will try to keep the thread updated.
Altera_Forum
Honored Contributor
12 years ago
Thanks for the document. According to the advanced synthesis cookbook, similar information should be available for Stratix.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
Thanks, i think you pointed me to the right direction. I found a documentation which wasn't easy to google but describes how to set the LE in arithmetic mode and how to define the LUT tables (attached). I will try to keep the thread updated.
--- Quote End ---

It's very useful for TDC design. I'm also search these detail materials about LE, but i found nothing.

BTW, i have finished TDC design with altera's devices as attahced files show. The cin to cout delay should be 51ps from TimeQuest report. And the actual time should be different because of the gaps inside LAB and between LABs. We can see that the delay cell's min delay time is below 20ps, however, the max is about 170ps.
multiple-attachments.zip113 KB
Altera_Forum
Honored Contributor
12 years ago
Also, i found that we can't use carry and carry_sum directly in new version QII software. They will be optimized away when the project is compiled! It's very strange. I found some comments from altera's paper that we should can use them. But that paper is very old, maybe it is ok in old version QII. Even though, LCELL still can be used.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
BTW, i have finished TDC design with altera's devices as attahced files show. The cin to cout delay should be 51ps from TimeQuest report. And the actual time should be different because of the gaps inside LAB and between LABs. We can see that the delay cell's min delay time is below 20ps, however, the max is about 170ps.
--- Quote End ---

The additional delay involved with LAB boundary crossing already matters when creating regular LCELL delay lines, as shown in an empirical example. http://www.alteraforum.com/forum/showthread.php?t=27284

My conclusion from this experiment is that it's difficult up to impossible to create uniform delay lines in FPGA. You would need to control exact LE placement and routing which is apparently beyond the purpose of Quartus and no regularly available feature (at least not in a straightforward way).

--- Quote Start ---
Also, i found that we can't use carry and carry_sum directly in new version QII software. They will be optimized away when the project is compiled!
--- Quote End ---

Do you have a simple carry primitive example that has been working in previous Quartus versions and isn't working no more?
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
The additional delay involved with LAB boundary crossing already matters when creating regular LCELL delay lines, as shown in an empirical example. http://www.alteraforum.com/forum/showthread.php?t=27284

My conclusion from this experiment is that it's difficult up to impossible to create uniform delay lines in FPGA. You would need to control exact LE placement and routing which is apparently beyond the purpose of Quartus and no regularly available feature (at least not in a straightforward way).

Do you have a simple carry primitive example that has been working in previous Quartus versions and isn't working no more?
--- Quote End ---

1. You are right, the DNL is very bad if you use lcell implement delay-line inside FPGA. But i used carry-chain to implement delay-line. The DNL is much better than lcell shown in my previous post. I think it's ok if your resolution won't be more than 180ps. If you need measure time more accurate than 170ps, such as resolution below 100ps, there are digital method for increase the resolution based above raw bin. I attched the improved DNL result, the red is the raw bin, and the blue shape is the improved DNL. Now the resolution is increased to 65ps. Also you can still increase resolution much more, such as you can increase and get 10ps resolution.

2. For the carry primitive example, i didn't implement in old version Quartus, but i got the imformation from an old PPT from altera, which said we can implement carry or carry-sum directly.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
Thanks, i think you pointed me to the right direction. I found a documentation which wasn't easy to google but describes how to set the LE in arithmetic mode and how to define the LUT tables (attached). I will try to keep the thread updated.
--- Quote End ---

Hi SiA_Schumi:

Do you find the other two files mentioned inside file cycloneii_le_wys.pdf. Which are stratixii_le_wys.doc and stratix_wysuser.doc.doc?
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
1. You are right, the DNL is very bad if you use lcell implement delay-line inside FPGA. But i used carry-chain to implement delay-line. The DNL is much better than lcell shown in my previous post. I think it's ok if your resolution won't be more than 180ps. If you need measure time more accurate than 170ps, such as resolution below 100ps, there are digital method for increase the resolution based above raw bin. I attched the improved DNL result, the red is the raw bin, and the blue shape is the improved DNL. Now the resolution is increased to 65ps. Also you can still increase resolution much more, such as you can increase and get 10ps resolution.
--- Quote End ---

The objective of my experiment was different, not aiming to high resolution rather than a uniform medium resolution. I know that carry chain can achieve a higher resolution. The problem of non-uniform steps (TDC DNL) due to routing delays shows nevertheless. And as far as I see, it's difficult to control the routing delay effects intentionally.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
Hi SiA_Schumi:

Do you find the other two files mentioned inside file cycloneii_le_wys.pdf. Which are stratixii_le_wys.doc and stratix_wysuser.doc.doc?
--- Quote End ---

google for "Cycloneii_le_wys.pdf" and on the first hit u can find those documents. (somehow not allowed to post links here...)
That is where I found this files and they also have the stratix version.

BTW, considering some papers, it seems like they do not use the cin cout ports(through 1 LUT), but just the multiplexers. Compare the appended paper with the LCELL circuit.

However this was just a minor idea of mine and I had to move on to a different project. I will try to pick it up again once i have time.

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Designing with low level primitives

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