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... It shows some parts of my design which are not able to run at 50MHz but at say 35-45 MHz. Now, all these paths Quartus marked red, they actually don't have to run at 50 MHz but they have to have their states stable every second clock which would mean they only have to run at 25MHz...
But when Quartus says that there are paths that only can run at max 35MHz and I only need them to run at 25MHz, then everything should be OK, right?
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If you did the divide-by-2 with a clock enable, then you can use a multicycle setup of 2 to tell the timing analyzer that 2 clock cycles are allowed. For a clock enable divide-by-2, you also need a multicycle hold of 2 with the Classic Timing Analyzer (which you probably have by default if you are using that analyzer) or a multicycle hold of 1 with TimeQuest (which is not the default with that analyzer).
There are ways other than a clock enable for the multicycle to be appropriate, but it must be a method that guarantees that the input to the destination registers will not be changing at the clock active edges where you don't want the registers to update their value. The clock enable signal makes the register D input be completely ignored at those clock edges.
If you don't have time to figure out right away how to do the multicycle constraints, then it is OK to manually check that the paths that are allowed 2 clock cycles are actually fast enough.
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