Design works on Quartus 7.1 but not 4.2

Rysc and Brad,

thanks for your usefull hints!

Today, I printed the Quartus manual chapter about Signal Tap II in order to read it during the weekend. I agree, that I have to dive a little deeper into design, debugging and constraints for FPGA development.

In my big design (the one I currently work on to finish soon), I set my clock constraints to 50MHz. And you are right, that Quartus informs me about paths that do not fit this constraint. It shows some parts of my design which are not able to run at 50MHz but at say 35-45 MHz. Now, all these paths Quartus marked red, they actually don't have to run at 50 MHz but they have to have their states stable every second clock which would mean they only have to run at 25MHz. One day, I tried to tell Quartus this in its constraint settings but I failed due to my weak knowledge about this stuff. Seems that I have to print out the constraint parts of the manual next weekend ;)

But when Quartus says that there are paths that only can run at max 35MHz and I only need them to run at 25MHz, then everything should be OK, right?

Nevertheless, that has nothing more to do with the post topic. It seems that I have to expand my knowledge boundarys . . . Usefull hints and explanations as yours above are allways welcome.

Regards,

Maik