Design works on Quartus 7.1 but not 4.2

Timing constraints tell Quartus how to optimize placement, routing, delay chains, etc. Now, in the simple case you might answer "as fast as possible", but it can be much more complex than that. If you have more than one clock, then there may be decisions that trade off performance in one domain for another, and accurate timing constraint reflect that. IO constraints can be even trickier. For example, on your input side, you need the data to get ther before the latching clock, but you also need to be careful of the flip-side, when the data gets there before the launching clock edge(a hold violation). Users often say, I'm running my design very slow, it should work, but hold violations are valid even at 1Hz.

If you're using the Classic Timing Analyzer(which you'd have to be in Q4.2), just by a global clock constraint and a tight Tsu/Tco constraint(say 5ns). It may not pass, but having the best Tsu/Tco is probably the solution that would solve the largest number of designs(I have no idea if it's what's affecting yours). The bottom line is that nobody can really diagnose the issue without knowing what's wrong(at a lower level then Q4.2 doesn't work). As I mentioned, some of the things I've seen are things no one but the actual designer could have ever resolved, because they were very design specific.