Design works on Quartus 7.1 but not 4.2

Hi Maik:

I didn't see anything definite in the code, but again, I'm use verilog as my default language, so I may miss something in VHDL.

But since you seem to be using only the 50 MHz clock, and the slower UART Baud rate is done by a clock enable, I thing you should be ok for most of the issues RSYNC described, unless the 50 MHz clock was not defined and for some reason Quartus 4.2 was compiling the design to run very slowly. (unlikely).

On thing I do see however, is on the RX data path, you are using the RX input directly without double registering it. This could cause metastability issues, because the setup/hold to the 50 MHz would be violated. Is this the cause of your problem? Probably not, but it's something worth fixing.

Pete