Design works on Quartus 7.1 but not 4.2

Hello anakha!

Thanks for your reply!

I'm sorry that I didn't express myself clearly in the first post.

It compiles in both versions correctly (no syntax errors). During compiling I got the same messages in both Quartus Version. Even the warnings are the same and tell me that some bits of my databyte stuck to ground as I ever send the same byte via the uart and it has some zero bits in it. The problem is, that the Quartus 7.1 .sof file works as expected, and the Quartus 4.2 .sof-file does not work on one and the same FPGA. . . .

Well, if you want to see the code, I put it in in the attached zip-File. If you (or someone else) want to compile it on your Quartus Version, I would be happy if you send the .sof file here, so that I can try it on my boards.

For the EP1S10F780C6ES device, my pin assignments are: clk - K17, txd - U21, rxd - Y28

For the EP1S25F672C7 device, my pin assignments are: clk - B12, txd - F25, rxd - K24

Unused pins have to be 'input tri-stated', as it is an development board I am using.

My clk frequency is 50MHz in both cases.

Still, I have no idea, why it just don't work with Quartus 4.2 and would be happy if you can help me.

Greets,

Maik