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Altera_Forum's avatar
Altera_Forum
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10 years ago

Design Unit Not Found

Hello all,

I'm still trying to get my *first* simulation running with ModelSim, and my progress is quite limited. I think I have my license issues worked out finally, after talking directly to Altera support.

Currently, I am trying to run simulations on my project, but am getting errors. whenever I try to simulate anything (right click on module in my work dir and select simulate), I get the following: 

ModelSim> vsim work.TX_PLL# vsim work.TX_PLL #  Start time: 17:52:30 on Mar 09,2016#  Loading work.TX_PLL#  ** Error: (vsim-3033) D:/Users/Nicholai/Desktop/Research/QuartusII/March2016/DACSimulation/TX_PLL.v(75): Instantiation of 'altpll' failed. The design unit was not found.#     Time: 0 ps  Iteration: 0  Instance: /TX_PLL File: D:/Users/Nicholai/Desktop/Research/QuartusII/March2016/DACSimulation/TX_PLL.v#          Searched libraries:#              D:/Users/Nicholai/Desktop/Research/QuartusII/March2016/DACSimulation/simulation/modelsim/rtl_work#  Error loading design#  End time: 17:52:31 on Mar 09,2016, Elapsed time: 0:00:01#  Errors: 1, Warnings: 0

I found a lot of threads with similar problems, but haven't figure out the solution. I am not sure where the library for 'altpll' is. I do have a huge list of libraries in the library pane. Is there an easy way to know what library my cores are from? Once I figure out what library altpll is in, when do I use the include directory command? Should that go in my .do file? Not a single one of my modules will simulate- I am using:

ROM: 1-Port

LPM_COUNTER

ALTDIDO_OUT

ALTPLL

I am using a Stratix IV device.

Sorry if this is a very easy question to answer, I have never used this tool (or hardly any Altera tools) before. Right now, I have nothing set up and working. I'd like to get to the point where I have a testbench.

Thank you,

FrenchyRaoul

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --- Quote Start ---

    Hello,

    No. .vht stands for VHDL test bench file while vlog command compiles Verilog source code and SystemVerilog source codes. Hence it will not work.

    You should try following :

    1. In Quartus, Go to Assignments -> Settings... -> EDA Tool Settings -> Simulation.

      In that select 'Verilog' under 'Format for Output Netlist'.

    2. In Quartus, Go to Processing -> Start... -> Start Test Bench Template Writer

      This should now create dac_top.vt file in same folder in which dac_top.vht file was being created before.

    3. Now try following command: vlog -reportprogress 300 D:/Users/

    We would like to know what happens with this.

    Thank you,

    Bhaumik

    --- Quote End ---

    Bhaumik, you have proven yourself very helpful (and generous) with your help. I think I am very close to having a working test bench. Here is the output of your steps: 

    vlog -reportprogress 300 D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/simulation/modelsim/dac_top.vt# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015#  Start time: 21:03:15 on Mar 28,2016#  vlog -reportprogress 300 D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/simulation/modelsim/dac_top.vt #  -- Compiling module dac_top_vlg_tst#  #  Top level modules:#  	dac_top_vlg_tst#  End time: 21:03:16 on Mar 28,2016, Elapsed time: 0:00:01#  Errors: 0, Warnings: 0
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    @ mikedsouze,

    Thank you for sharing idea about vcom command. It could have solved problem more easily.

    @ FrenchyRaoul,

    We are glad to hear that you are close to your goal.

    Cheers,

    Bhaumik
  • Logic5150's avatar
    Logic5150
    Icon for New Contributor rankNew Contributor
    5 years ago

    Another possible cause of this error is when you have your top level name and the corresponding file name different from the module name .

    For example,
    TOP_LEVEL_NAME=testbench, corresponding file name=testbench.sv.
    module you declared inside testbench.sv=module testbench_top;.