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Hello,
No. .vht stands for VHDL test bench file while vlog command compiles Verilog source code and SystemVerilog source codes. Hence it will not work.
You should try following :
- In Quartus, Go to Assignments -> Settings... -> EDA Tool Settings -> Simulation. In that select 'Verilog' under 'Format for Output Netlist'.
- In Quartus, Go to Processing -> Start... -> Start Test Bench Template Writer This should now create dac_top.vt file in same folder in which dac_top.vht file was being created before.
- Now try following command: vlog -reportprogress 300 D:/Users/
We would like to know what happens with this.
Thank you,
Bhaumik
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Bhaumik, you have proven yourself very helpful (and generous) with your help. I think I am very close to having a working test bench. Here is the output of your steps:
vlog -reportprogress 300 D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/simulation/modelsim/dac_top.vt# Model Technology ModelSim ALTERA vlog 10.4b Compiler 2015.05 May 27 2015# Start time: 21:03:15 on Mar 28,2016# vlog -reportprogress 300 D:/Users//Desktop/Research/QuartusII/March2016/DACSimulation/simulation/modelsim/dac_top.vt # -- Compiling module dac_top_vlg_tst# # Top level modules:# dac_top_vlg_tst# End time: 21:03:16 on Mar 28,2016, Elapsed time: 0:00:01# Errors: 0, Warnings: 0
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