design of a difficult VHDL Arithmetic and Logic Unit (ALU)

I think one of the main problems with your code and comments is that you have several unimplemented cases that say set Acc to something or increment Acc. Acc cannot be set to anything because it's an input. Either you have the comments wrong and you actually mean something else, or you're trying to do something that you cannot.

You also have 3 signals misleadingly called "RegN", when only Reg3 is actually a register. Reg1 and Reg2 are just wires connected to Acc and Data_reg inputs, and all Reg3 does it connect directly to the output. So first thing is you probably want to make Reg1 and Reg2 actual registers, and maybe only load the output in specific cases?