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Altera_Forum
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13 years ago

design of a difficult VHDL Arithmetic and Logic Unit (ALU)

Hey guys, I was wondering if someone could give me a hand with designing a specific ALU. Here are the main bits which I would like to implement: - sequentlial unit with 2 registers (e.g. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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- How can I'd declare reg1-3 as unsigned?

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signal Reg1,Reg2,Reg3 : unsigned(7 downto 0);