design of a difficult VHDL Arithmetic and Logic Unit (ALU)

I think you're on the right approach.

One thing, with numeric_std (good to see you're using it) std_logic_vectors are just collection of bits so it

doesn't know how to 'add' them etc ....

I'd declare reg1-3 as unsigned then ..

op <= std_logic_vector(reg3);

..to assign the result as a std_logic_vector.

Can you get hold of modelsim and play about with different combinations of operation? It'll help you see what's

going on.

Nial.