Design Flow Tips for Obtaining High Fmax as FPGA Gets Full

Thank you for all the expert advice!

My project is part of a 2 person team. I designed the lower level blocks that get instantiated 6 times into the top level. Another engineer designed a few other parts of the chip, and has been in charge of putting everything together at the top level as well. Since he has been away from work for the past few days, I copied the design from his computer and have been trying to make sense of it myself. I have been experimenting a little with partitioning and yesterday I was able to get a compile whereby the slowest part of my design gave me an Fmax of 140MHz. The only timing violation right now has nothing to do with the logic that I designed, so I may have to wait until my fellow engineer gets back to work to proceed further. Part of me wonders if the constraints placed on this other engineer's logic (triple speed Ethernet and other stuff) was interfering with my own logic constraints or chip resources....