Design Flow Tips for Obtaining High Fmax as FPGA Gets Full

Are all of the block inputs and outputs registered? If not then when you compile the block by itself (all I/O external) the non-registered I/O timing paths will not be reflected in the fmax result. But when you instantiate the blocks and interface them with other logic inside the design, the interface timing now comes into play. The timing inside the block may be fine and it's the interface timing that has become limiting. You should be able to see this quickly in the timing reports.

If that's what is going on you'll need to register the inputs and/or outputs that are not meeting timing. This is also an answer to how to maximize fmax: Register the inputs and outputs of all blocks in the design.