Honored Contributor
Honored ContributorYou're approach sounds good and is probably the best design technique there is. That doesn't mean things can't break when stitched together. I might build a cross-bar mux that runs at 177MHz by itself, but when I hook it up to the transceivers on both sides of the device, it now spreads across the die and fails timing. There are a number of things that can go wrong when stitching things together, but it's really hard to plan for them and I would recommend your approach.
The question is why is your path now at 120MHz, which is a big drop-off. I assume you're getting worse place-and-route, so spend some time in TimeQuest comparing the fit of these paths before and after. What's changed. Right-click on the six hierarchies in the Project Navigator and locate to Chip Planner and see how they're placed. Could logic be getting merged between these hierarchies? Do they connect in a way that forces them to be spread out, i.e. a topology where everyone talks to everyone and there's not good data flow? Is the device really full and Quartus is just barely able to get a fit, let alone maintain good timing?
