Design doesn't fit because of insufficient LAB

You're still significantly over. Logicu Utilization is the key metric as it tries to incorporate all the dynamic issues of fitting logic, and it's at 118%. (Which is the same as the LAB overuse, but gives more info). You really need to remove logic. Your register count is almost at 100%, but not every register will be usable due to lab-wide control signals,# -lab inputs, etc. It is interesting that your register count is higher than your LUT count. Usually it's the opposite. If your design is really, really heavily pipelined, then its possible. Maybe look through the hierarchy brower and look for register counts and ALUT counts and see if there are any really large outliers, which might be a RAM that didn't get inferred. Probably not there, but worth a check. But most likely you have to remove logic or go to a larger part, I'm sorry to say.