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Altera_Forum
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17 years ago

Design compiler integration

I tried to use dc with one of my designs and Altera's stratix ii gx library.

I specified constraints (clock, reset wires, false paths, etc), and got it to compile. However, timing is horrible (some points have 40ns delay - probably due to fanout, but I've had the design running with a 10 ns clock when synthesized with quartus), and it appears to use almost twice as much area as quartus's netlist (assuming the area reported by dc is in LUTs).

Has anyone else had experience in using dc with quartus? Did you find similar issues? Do you need to optimize post-synthesis to acheive your timing closure?

Thanks,

baver

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    --- Quote Start ---

    I tried to use dc with one of my designs and Altera's stratix ii gx library.

    I specified constraints (clock, reset wires, false paths, etc), and got it to compile. However, timing is horrible (some points have 40ns delay - probably due to fanout, but I've had the design running with a 10 ns clock when synthesized with quartus), and it appears to use almost twice as much area as quartus's netlist (assuming the area reported by dc is in LUTs).

    Has anyone else had experience in using dc with quartus? Did you find similar issues? Do you need to optimize post-synthesis to acheive your timing closure?

    Thanks,

    baver

    --- Quote End ---

    Hi,

    I'm not very familar with the Synopsys DesignCompiler, but why are using the DC?

    Is it a special version for FPGA's. If not, I would expect results like yours. If you use a synthesis tool , which is not aware of the special features (e.g. DSP blocks) and the routing structure you will get worse results.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    I thought Synopsys ended all FPGA support with their Design Compiler/FPGA Compiler tools, and subsequently purchases Synplify. That being the case, I would completely avoid using those tools to target an FPGA.