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I tried to use dc with one of my designs and Altera's stratix ii gx library.
I specified constraints (clock, reset wires, false paths, etc), and got it to compile. However, timing is horrible (some points have 40ns delay - probably due to fanout, but I've had the design running with a 10 ns clock when synthesized with quartus), and it appears to use almost twice as much area as quartus's netlist (assuming the area reported by dc is in LUTs).
Has anyone else had experience in using dc with quartus? Did you find similar issues? Do you need to optimize post-synthesis to acheive your timing closure?
Thanks,
baver
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Hi,
I'm not very familar with the Synopsys DesignCompiler, but why are using the DC?
Is it a special version for FPGA's. If not, I would expect results like yours. If you use a synthesis tool , which is not aware of the special features (e.g. DSP blocks) and the routing structure you will get worse results.
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