Forum Discussion
Altera_Forum
Honored Contributor
15 years agoI can share a simple deserializer utilizing DDIO:
chan:
FOR I IN 0 TO 7 GENERATE
lvds_rcv : altddio_in
GENERIC MAP (
intended_device_family => "Cyclone III",
invert_input_clocks => "ON",
lpm_type => "altddio_in",
power_up_high => "OFF",
width => 1)
PORT MAP (
datain => AD9222_D(I TO I),
inclock => fastclock,
dataout_h => dataout_h(I DOWNTO I),
dataout_l => dataout_l(I DOWNTO I));
PROCESS (fastclock)
BEGIN
IF rising_edge(fastclock) THEN
lvds_sr(I) <= lvds_sr(I)(9 downto 0) & dataout_l(I) & dataout_h(I);
END IF;
END PROCESS;
PROCESS (slowclock)
BEGIN
IF reset = '1' THEN
lvds_rx(I) <= (others => '0');
ELSIF rising_edge(slowclock) THEN
lvds_rx(I) <= lvds_sr(I);
END IF;
END PROCESS;
END GENERATE;