derive_pll_clocks command

When derive_pll_clocks is run, you'll see an Info message in TimeQuest that shows the exact create_generated_clock commands being run, so that's exactly what is going on under the hood. Just cut-and-paste from those into your .sdc and change the -name option.

(You'll note that the -source option describes the pin going into the PLL, not the top-level port. This is perfectly legal in TimeQuest and gives the same result as if you had used the top-level port(assuming the PLL is driven by the port). The beauty of doing this is the tool doesn't have to know the top-level port, you can change its name or hook it up to something else like the output of another PLL, and the command still works. It's just something that looks "strange" the first time you see it.)

Thanks.....I keep forgetting about the tcl commands showing up within Quartus II and TimeQuest. I prefer to use these tcl commands, albeit with a more readable clock name, than just using a single command.

I've found that in order to completely understand which PLL output is attached to which signal name in the schematic, I need to refer back to SOPC Builder. For example, pll.c0 is <pll_instance_name>.clk[0], and from SOPC Builder, you can see which clock name was used whenever the PLL wizard was used. Why TimeQuest doesn't use these clock names for the -name option, I don't know.

I agree that it's a little unusual to see the -source option used that way. If I traced this in the Verilog generated netlist, I would probably find that this signal is coming from the input clock pad or the output of boundary scan cells or some other input pad test logic.

Thanks again for the heads up on the tcl commands.

Tony