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Altera_Forum's avatar
Altera_Forum
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14 years ago

derive pll clock

My sdc file has a derive_pll_clock to constrain the pll output clocks. How do I use the pll output 0 clock to constrain an input signal. I have tried the following which does not work ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi,

the derive_pll_clocks will create the output clocks.

They have ugly names but if you need to refer to a PLL output in your constrains, that's what you should use.

The PLL output clock name is something like {my_pll_instance|altpll_component|pll|clk[0]}]

Anyway, you should not constrain the input based on the PLL clock. Instead, you should create a virtual clock and constrain the input based on it.