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(1) Is it possible to maintain
temporal accuracy (down to very few nanoseconds) when using a FIFO buffer to delay one of the incoming signals, or will sending the signals into the buffer lose that accuracy and only share rising/falling edges with my clock? (Does the buffer say that block of data is either entirely zero or entirely 1, depending on whether the signal was in a high or low state at the rising edge of the clock when it collects the data?)
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This is going to be the tricky part ... to maintain 2ns sampling accuracy requires a 500MHz clock to the sampling circuit (or 3ns at 333MHz). Depending upon the device this may or may not be achievable; it is at the high (or beyond) end of most device PLLs.
The maximum clock tree frequency for the C6 (fastest) speed grade CycloneIV device (as used on a DE2 board) is listed as 500MHz. So it will be quite a challenge for you to do that.
Honored Contributor
