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Altera_Forum's avatar
Altera_Forum
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18 years ago

Delay Time in VHDL

Hi ..

I need your help.I am beginner in this field.

I am using Altera FPGA board and it has 24mhz clock frequency and now i want 62 micro second delay time in my application ..How can i make it delay ??

If u have code or something like this then it will be better to undestand for me..

Thanks a lot..

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    If you want it to occur every 62us, you can use a counter to count out the number of clock ticks there are in 62us (you do the math), and then set up some combinational logic to flag when the counter is at that number.

    There is a counter in the Mega Plug-in Wizard that you can use.