delay part of a clock cycle

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Hi Mr. kaz

thank you for your reply

the idea is that i have two signal from two process

and i used them in a third process

but these two signal arrive after some part of the clock cycle

so i want to delay the action to some percent of the clock cycle (after 10% of the rising edge)

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you sample each of two signals on same one clk edge and sample result on next edge of same clk. All fpga design is based on sampling on clk edge and expecting decision to arrive at next clk edge. Inserting micro delays is not possible in current technology of FPGAs.