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Altera_Forum's avatar
Altera_Forum
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11 years ago

delay part of a clock cycle

Hello i have a question is how to generate a delay for part of a clock cycle (for example after 0.1 of the clock cycle), since I couldn't use the wait for command for synthesis is there any way ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

What is the point of delay?

The fitter will insert delay from clk edge out of control as long as it passes timing. The whole idea of clk is to sample at its edge.