Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

delay part of a clock cycle

Hello

i have a question is how to generate a delay for part of a clock cycle (for example after 0.1 of the clock cycle), since I couldn't use the wait for command for synthesis

is there any way to do that in VHDL inside a process

for example

i want to make

a <= b; but after 0.1 of the clock cycle passed, not exactly at the rising edge

please if any one can help

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    You could use a PLL to generate a phase-shifted version of your clock then pass data between the clock domains, but with a phase shift of only 10% of the clock period it may be tough to meet the setup time of the second register depending on your clock frequency. A 10x clock (also generated using a PLL) would be another option. Without more information on what you're trying to do and how fast you're running that's the best I got.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    What is the point of delay?

    The fitter will insert delay from clk edge out of control as long as it passes timing. The whole idea of clk is to sample at its edge.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hi Mr. kaz

    thank you for your reply

    the idea is that i have two signal from two process

    and i used them in a third process

    but these two signal arrive after some part of the clock cycle

    so i want to delay the action to some percent of the clock cycle (after 10% of the rising edge)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    Hi Mr. kaz

    thank you for your reply

    the idea is that i have two signal from two process

    and i used them in a third process

    but these two signal arrive after some part of the clock cycle

    so i want to delay the action to some percent of the clock cycle (after 10% of the rising edge)

    --- Quote End ---

    you sample each of two signals on same one clk edge and sample result on next edge of same clk. All fpga design is based on sampling on clk edge and expecting decision to arrive at next clk edge. Inserting micro delays is not possible in current technology of FPGAs.