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Altera_Forum's avatar
Altera_Forum
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18 years ago

delay in output

Hi all, I run P&R in quartus and get *.vho, *.sdo after running timing simulation of this ram implementation if rising_edge(clk) then if wr_en='1' then ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hi Brad,

There are examples in precision manual (coding style - memory)

using address_save...

I understood my mistake...

I forgot to analyze the tco!! and that why I got the output with delay of some ns...

hope that I right...

what do you think on using address_save? Is is a good way to stabilize the address signal?

tenx

ari