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Altera_Forum's avatar
Altera_Forum
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16 years ago

Delay between modules

Hi guys, I am working on a project that has 2 modules connected in the design. I'd like to place an intentional delay between the lines that connect the two modules, how can I do this? ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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There is no reliable way to implement analog asynchronous delays inside an FPGA, if that's what you mean.

It is not totally impossible, you can use dummy combinational gates, and also force artificially long routing. But neither the hardware neither the tools were designed for this purpose.

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Ah, I see vj, thank you. My next question would be...can I find out the delay of a combinational gate? Let's say I want to use NAND gates to model the delay, how could I find out the delay of that particular NAND gate used in quartus?

Also, I saw this thread: http://www.alteraforum.com/forum/showthread.php?t=3068

For that method in that thread, can I do this between two modules? I notice for that design that Rysc uploaded he used purely a BDF file, but I only have 2 Verilog files.

Thank you so much guys.

-JV