degedge count problem..

Hi, I have a very simple verilog code. But I get wrong result. When I look through the oscilloscope, I see 10 negative edges. But the result I get with a simple code that I write is sometimes 12, sometimes 13 or even more. The yellow graphic is scl..

reg[15:0] scl_clock_count=0;

always @(negedge scl)

scl_clock_count <= scl_clock_count + 1'b1;