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Altera_Forum
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8 years ago

degedge count problem..

Hi, I have a very simple verilog code. But I get wrong result. When I look through the oscilloscope, I see 10 negative edges. But the result I get with a simple code that I write is sometimes 12, som...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

What is SCL? is it the clock from an SPI bus? for this, usually it is safer to use a fast system clock and sample the SCL with the fast system clock.