defparam issue vqm

Hello,

I face a new issue with Quartus prime pro (together with a .vqm from Synplify), I did not have this issue with Quartus 13.1 (same RTL code) for the stratix 3. What shall I do?

RTL Module:

module rng4_sa_intg #(
APB_WIDTH = 12
) (

// FPGA Clock
`ifdef ID_CFG_DTRNG_FPGA // FPGA support
input logic ip_fpga_ringo_clk,
`endif // ID_CFG_DTRNG_FPGA // FPGA support

input logic clk_and_reset_p_pclk,
input logic clk_and_reset_p_rstn,
...

Instantiation in RTL (black box in that project, the rng4_sa_intg is in another .vqm)

rng4_sa_intg #(
.APB_WIDTH(12)
) u_trng (

`ifdef ID_CFG_DTRNG_FPGA // FPGA support
.ip_fpga_ringo_clk (free_running_48mhz_clk),
`endif // ID_CFG_DTRNG_FPGA // FPGA support

.clk_and_reset_p_pclk (rng_apb_clk),

.vqm content (stratix10_fpga_a_mix.vqm):

rng4_sa_intg u_trng (
.ip_fpga_ringo_clk(free_running_48mhz_clk),
.clk_and_reset_p_pclk(rng_apb_clk),
...
.test_p_async_disable(GND)
);
defparam u_trng.APB_WIDTH=12;
// @1005:9418

other .vqm with the rng4_sa_intg block (rng4_sa_intg_stratix10.vqm):

/* Synopsys
.origName=rng4_sa_intg
.langParams="APB_WIDTH"
APB_WIDTH=12
*/
input ip_fpga_ringo_clk ;
input clk_and_reset_p_pclk ;

.....

Using Synplify R-2021.03 + patch.

Quartus prime pro 21.1.0 error:

Error(14394): Verilog HDL error at stratix10_fpga_a_mix.vqm(3013071): APB_WIDTH is not declared under the prefix "u_trng"
Error(16186): Can't elaborate top-level user hierarchy

I use in the .qsf:

set_global_assignment -name VQM_FILE ../../rng4_sa_intg/synplify/synthesis/rng4_sa_intg_stratix10.vqm
set_global_assignment -name VQM_FILE ../../stratix10/synplify_synth_quartus_fit/synthesis/stratix10_fpga_a_mix.vqm

Kind Regards,

Alex.