Define internal signal as a base clock?

I wonder whether the information at http://www.altera.com/support/kdb/solutions/rd04202001_2747.html is correct (I used the feedback form on that page to ask about that). In 2004 (before that on-line solution was last updated), an authoritative source at Altera said, "The chips themselves guarantee that when a single input to a look-up table changes, the output will not glitch." This statement applied to all 4-input-LUT-based device families up through at least the original Stratix plus MAX II.

The person who made that statement did not determine whether the same thing applied to ALUT families (Stratix II, Stratix III). Maybe http://www.altera.com/support/kdb/solutions/rd04202001_2747.html was supposed to say it was for ALUTs (not 4-input LUTs). That on-line solution is about a 4-to-1 multiplexer. For that size mux to fit in a single look-up table, it has to be in an ALUT.