Define internal signal as a base clock?

Thanks for the tips guys, much appreciated :) These are the sorts of things that are hard to pick up when you have to teach yourself VHDL!

I'm reasonably happy that my derived clock, and the mechanism I'm using for passing signals between clock domains, is robust - it has been shipping in volume for several years now. The code fragment above is just an example to illustrate a point, of course - the real code is much more complicated.

If you're certain that TimeQuest would be able to better understand what I'm trying to achieve, then maybe the time has come (if you'll pardon the expression) for me to try it out. I just don't want to spend ages learning a new tool only to be confronted with a new error message that means the same thing as the old one!